The present invention relates to methods of fabricating power semiconductor devices, and more particularly to a single mask method of making a cellular thyristor semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels.
Thyristor semiconductor power devices are well known in the art and include a variety of device types. For example, and with reference to FIG. 1, a MOS controlled thyristor (MCT) 10 may include numerous operating cells 12, each with an Off-FET for turning the device off, and fewer On-FETs with drains 14 for turning the device on, which may be surrounded by transition cells 16. Application of specific voltages to a gate 18 turns the MCT on or off by operating the Off-FETs or On-FETs. Operation and application of such devices is known to those of skill in the art.
As is typical, operating cells 12 are in an N type base 20 which is on a P type layer which has a P type base 22 and an optional buffer layer 24. The P type layer is atop an N+ layer 25 which is an emitter of an NPN wide base bipolar junction transistor comprising layer 25 which is the NPN emitter, P layers 22 and 24 which are the NPN base, and N base 20 which is the NPN collector. Each operating cell 12 includes a P type well 26 having a P+ region 28 and an N+ source region 30 therein. The P type well 26 and P+ region 28 form an emitter of a PNP bipolar junction transistor which also includes N type upper base 20 (the PNP base) and P type base 22 (the PNP collector). Source region 30 is the Off-FET source, N type base 20 is the Off-FET drain, and the gap therebetween forms the Off-FET gate controlled channel region 32. A P type well 34 in transition cell 16 is the On-FET source, a portion 14 of the P type base 22 at the substrate surface is the On-FET drain, and the gap therebetween is the On-FET gate controlled channel region 36.
Such devices work well, but can be improved in both manufacturability and in performance. Semiconductor devices are fabricated in multi-step processes in which each step is costly and time consuming. The need for each step is carefully analyzed and steps are eliminated or consolidated whenever possible. The cost and time saved by elimination of even a single step makes a process in which such an improvement is found a valuable asset.
One of the ways the number of steps can be reduced is by reducing the number of masks which are used to form the cells. As is known, one mask may be used for several sequential steps in what are denoted self-aligned processes. For example, U.S. Pat. No. 5,045,903 to Meyer, et al. and U.S. Pat. No. 5,528,058 to Pike, Jr., et al. disclose single mask processes. The latter of these patents discloses a process by which portions of cells of an MCT may be fabricated with a single mask, but in which an upper layer is formed epitaxially. This additional epitaxial growth step is desirably avoided. As will be discussed, in an embodiment of the present invention a single mask is used to form the cells and to form the upper bases and On-FET drains of the device, a feature not suggested in the prior art. The same mask may also be used to form floating field rings at the periphery of the device.
One of the areas in which the performance of such devices can be improved is in device turn-off. One of the ways that device turn-off can be improved is by increasing the density of Off-FET channels 32. As may be seen in FIG. 1, if the number of cells per unit area can be increased by making the cells smaller, the density of Off-FET channels will increase. However, the lateral arrangement of the cells and the practical problem of manufacturing tolerances have heretofore limited the sizes of cells. For example, smaller cells and more densely populated cells require more precise alignment of the process performed in each step. The present invention uses a self-aligned process which can make smaller cells, thereby improving the turn-off performance of cellular gated semiconductor power device, such as an IGBT or MCT.
Accordingly, it is an object of the present invention to provide a novel method of fabricating a thyristor semiconductor device which uses a single mask, reduced diffusion process and thereby obviates the problems of the prior art.
It is another object of the present invention to provide a novel method of fabricating a semiconductor device that is operated with On-FETs and Off-FETs and in which a single mask is used to form cells in the device and to form upper bases of three-layer bipolar transistors and drains of On-FETs in the device.
It is still another object of the present invention to provide a novel method of fabricating a MOSFET controlled, four-layer semiconductor device in which a single dopant-opaque mask is used to form all structure above the bottom two layers of the device, including the upper portions of two three-layer bipolar transistors which form the four-layer device and On-FETs and Off-FETs which operate the device.
It is yet another object of the present invention to provide a novel method of fabricating an PNPN semiconductor device whose operation is controlled with On-FETs and Off-FETs, in which a single dopant-opaque mask, which sits atop a P layer which is atop an N layer, has first openings spaced apart so that a diffusing N type dopant merges in adjacent first openings to form upper bases of PNP transistors in which the P layer is a collector, and second openings spaced apart so that the diffusing N type dopant does not merge in adjacent second openings to thereby form P drains of On-FETs, and in which N layer is an emitter of NPN transistors having the upper bases as collectors.
It is a further object of the present invention to provide a novel method of fabricating a semiconductor device that is operated with On-FETs and Off-FETs in which a single mask is used to form upper bases of three-layer bipolar transistors, drains of On-FETs, and floating field rings in the device.
It is yet a further object of the present invention to provide a novel method of fabricating a two-sided Fast Turn Off (FTO) semiconductor device that has On-FETs and Off-FETs on one side and at least an Off-FET on the other side in which each side is fabricated with a single mask.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.